xtensa-lx6-rt

Low level access for xtensa lx6 processors


Keywords
register, peripheral, xtensa, lx6
Licenses
MIT/Apache-2.0

Documentation

xtensa-lx-rt

Crates.io docs.rs Crates.io Matrix

Minimal runtime/startup for Xtensa LX processors. This crate currently supports the following CPU's:

Feature Supported CPUs
esp32 ESP32 (LX6)
esp32s2 ESP32-S2 (LX7)
esp32s3 ESP32-S3 (LX7)
esp8266 ESP8266 (LX106)

I get linker errors when I build for debug

Xtensa only provides a small code space for exceptions to fit inside, when building an unoptimized build the code size of a exception handler may exceed that size, causing a linker error. To fix this, you should always optimize this crate, even in debug builds. Adding the following to your projects Cargo.toml should do the trick.

[profile.dev.package.xtensa-lx-rt]
opt-level = 'z'

License

Licensed under either of

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.