Fixed Point for HDL

This module provides fixed point class for hdl simulation.

q format, fixed integer, fpga, verilog, systemverilog, vhdl

Basic Usage

FP(value, integer_bit, fractional_bit, sign)

>>> from fixedpoint4hdl import FP
>>> a = FP(1.5,3,4)
>>> a.hdl()
'logic  [2:-4] fp = 24 //1.5'
>>> a
FP( 1.5, 3, 4, False)
>>> a*a
FP( 2.25, 6, 8, False)
>>> a/a
FP( 1.0, 7, 7, False)
>>> a+a
FP( 3.0, 3, 4, False)
>>> a+3
FP( 4.5, 3, 4, False)
>>> a-3
Exception: FP( -1.5, 3, 4, False) :underflow
>>> a*3
FP( 4.5, 3, 4, False)
>>> a[0:-1]
3
>>> a.i
3
>>> a.f
4
>>> a.s
False
>>> a.f=0
>>> a
FP( 2.0, 3, 0, False)