bust bus tool
Utility for simply creating and modifying VHDL bus slave modules.
The main goal of the project is to able to automatically create and modify VHLD bus slave modules based on a simple definition format. By employing VHDL records the handling of the registers can be completely hidden in a module seperate from the rest of the designers logic. All referring to the registers are done via a record which specifies if the register is read-only or read-write, and also includes the name. All bus-specific signals are also wrapped in records. This increases the readability of the design as a whole.
bust currently supports these bus-types:
bust is thoroughly tested with python 3.6.8 but should work with the following versions:
- python 3.4
- python 3.5
- python 3.6
- python 3.7
- python 3.8
bust does NOT support python 2.7 and neither should you!
Install the latest relase by using pip:
pip install bust
bust.py FILE [-o DIR]
bust.py -h | --help
The examples folder contains JSON-files for the bus types supported. The files are human readable to the point that you can create your own from this template alone. The folder also contain the output files generated based on the JSON-files.
Simulations script are made solely for Modelsim/Questasim. For any other simulators you need to compile everything yourselves. All testbenches require UVVM - which can be cloned from their Github page.
See the example files for how you point to the specific folders.
Latest Development Version (Bleeding Edge)
The latest development version can be found in the dev branch on Github. Clone the repo and checkout the branch.
git clone https://github.com/olagrottvik/bust.git
git checkout dev
pip install -r requirements.txt
python -m bust
Release notes can be found at the Releases page.
This project is licensed under the MIT license - see LICENSE for details.