VUnit is an open source unit testing framework for VHDL/SystemVerilog.


Keywords
asic, fpga, systemverilog-hdl, testbench, unit-testing, universal-verification-methodology, verification, verilog-hdl, vhdl
License
MPL-2.0
Install
pip install vunit-hdl==4.6.0

Documentation

'docs' workflow Status 'images' workflow Status 'push' workflow Status 'coverage' workflow Status

VUnit is an open source unit testing framework for VHDL/SystemVerilog. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a test early and often approach through automation. Read more about VUnit.

Contributing in the form of code, docs, feedback, ideas or bug reports is welcome. Read our contribution guide to get started.