SystemVerilog


Total Packages: 26

Popular SystemVerilog Packages See more »

erroranalyzer
ErrorAnalyzer is the EDA tool of choice to understand and find simulation failures faster
Latest release 2.2.1 - Updated - 5 stars
axi_tdl
tdl 是一种硬件构造语言, 和chisel类似, 但是更加有趣, 他是一种基于Ruby的DSL. 最终它会编译输出systemverilog 。
Latest release 0.2.5 - Updated - 1 stars
enso-nic
Python frontend for the Ensō NIC.
Latest release 0.1.3 - Updated - 10 stars
Hast.Vitis.HardwareFramework
Hastlayer Hardware Framework - Xilinx Vitis: The hardware framework project to be used with the H...
Latest release 1.2.0 - Updated - 2 stars
ucdp-regf
Unified Chip Design Platform - Register File
Latest release 0.12.0 - Updated

New SystemVerilog Packages See more »

ucdp-common
Unified Chip Design Platform - Common Modules
Latest release 0.2.0 - Published
pybfms-generic-sram
pybfms_generic_sram provides bus functional models for the SRAM protocols
Latest release 0.0.1.20200226.3 - Published
pynqpandas
Hardware-accelerated Pandas
Latest release 0.0.1 - Published

Updated SystemVerilog Packages See more »

rtl-generator
Extensible RTL generator/parameterizer written in Python
Latest release 1.0.1 - Updated
ucdp-mem
Unified Chip Design Platform - Memories
Latest release 0.3.0 - Updated
ucdp-regf
Unified Chip Design Platform - Register File
Latest release 0.12.0 - Updated
ucdp-amba
Unified Chip Design Platform - AMBA
Latest release 0.8.1 - Updated
pythondata-cpu-ibex
Python module containing system_verilog files for Ibex cpu.
Latest release 0.0.post2937 - Updated - 2 stars

Most Depended upon SystemVerilog Packages

Hast.Vitis.HardwareFramework
Hastlayer Hardware Framework - Xilinx Vitis: The hardware framework project to be used with the H...
Latest release 1.2.0 - Updated - 2 stars

Top SystemVerilog Licenses

Apache-2.0 10 projects

MIT 7 projects

BSD-3-Clause 3 projects

GPL-3.0 1 project

GPL-3.0+ 1 project

LGPL-2.1 1 project

OML 1 project

Top SystemVerilog Package Managers

PyPI 23 projects

NuGet 1 project

Rubygems 1 project