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peakrdl-regblock
Release 0.22.0

Compile SystemRDL into a SystemVerilog control/status register (CSR) block

Homepage PyPI Python

Keywords: SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, Verilog, SystemVerilog, register, abstraction, layer, FPGA, ASIC, systemrdl-compiler, systemverilog-hdl
License: Other
Install: pip install peakrdl-regblock==0.22.0

Documentation

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

Dependencies: 2
Dependent packages: 1
Dependent repositories: 0
Total releases: 23
Latest release: 25 days ago
First release: Dec 5, 2021
Stars: 43
Forks: 26
Watchers: 14
Contributors: 8
Repository size: 918 KB
SourceRank: 10

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Releases

0.15.0: Jun 9, 2023
0.16.0: Jun 29, 2023
0.11.0: Mar 12, 2023
0.12.0: Apr 4, 2023
0.13.0: May 12, 2023
0.14.0: May 18, 2023
0.22.0: Apr 1, 2024
0.21.0: Mar 21, 2024
0.20.0: Jan 6, 2024
0.19.0: Oct 12, 2023

See all 23 releases

Contributors

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