SVUT is a very simple flow to create a Verilog/SystemVerilog unit test. It is widely inspired by SVUnit, but it's written in python and run with Icarus Verilog or Verilator. SVUT follows KISS principle: Keep It Simple, Stupid.

Hope it can help you!

SVUT is available on Pypi and can be installed as following:

pip3 install svut

Git clone the repository in a path. Set up the SVUT environment variable and add SVUT to $PATH:

export SVUT=$HOME/.svut
git clone https://github.com/dpretet/svut.git $SVUT
export PATH=$SVUT:$PATH

SVUT relies on Icarus Verilog as simulation back-end. Please install it with your favourite package manager and be sure to use a version greater or equal to v10.2. SVUT is tested with v10.2 and cannot work with lower version <= v9.x.

SVUT can also use Verilator with a limited support for the moment. A future release will improve it, with example & tutorial. SVUT is tested with version >= v4.

To create a unit test of a verilog module, call the command:

svutCreate your_file.v

No argument is required. SVUT will create "your_file_testbench.sv" which contains your module instanciated and a place to write your testcase(s). Some codes are also commented to describe the different macros and how to create a clock or dump a VCD for GTKWave or Surfer. A C++ file being the verilator top level is also generated (sim_main.cpp). It can be ignored if you don't use Verilator. An example to understand how to use can be found here

To run a test, call the command:

svutRun -test your_file_testbench.sv

or simply svutRun to execute all testbenchs in the current folder.

svutRun

SVUT will scan your current folder, search for the files with _testbench.sv suffix and run all tests available. Multiple suffix patterns are possible.

svutRun proposes several arguments, most optional:

• -test: specify the testsuite file path or a folder containing tests
• -f: pass the fileset description, default is files.f
• -sim: specify the simulator, icarus or verilator
• -main: specify the C++ main file when using verilator, default is sim_main.cpp
• -define: pass verilog defines to the tool, like -define "DEF1=2;DEF2;DEF3=3"
• -vpi: specify a compiled VPI, for instance -vpi "-M. -mMyVPI"
• -dry-run: print the commands but don't execute them
• -include: to pass include path, several can be passed like -include folder1 folder2
• -no-splash: don't print SVUT splash banner, printed by default
• -compile-only: just compile the testbench, don't execute it
• -run-only: just execute the testbench, if no executable found, also build it
• -fst: dump waveform with FST format. If not specified use VCD format

All these arguments are common for both the simulators.

Copy/paste this basic FFD model in a file named ffd.v into a new folder:

`timescale 1 ns / 1 ps

module ffd
    (
    input  wire aclk,
    input  wire arstn,
    input  wire d,
    output reg  q
    );

    always @ (posedge aclk or negedge arstn) begin
        if (arstn == 1'b0) q <= 1'b0;
        else q <= d;
    end

endmodule

Then run:

svutCreate ffd.v

ffd_testbench.v has been dropped in the folder from you called svutCreate. It contains all you need to start populating your testcases. In the header, you can include directly your DUT file (uncomment):

`include "ffd.v"

or you can store the path to your file into a files.f file, automatically recognized by SVUT. Populate it with the files describing your IP. You can also specify include folder in this way:

+incdir+$HOME/path/to/include/

Right after the module instance, you can use the example to generate a clock (to uncomment):

initial aclk = 0;
always #2 aclk = !aclk;

Next line explains how to dump your signals values into a VCD file to open a waveform in GTKWave (uncomment):

initial $dumpvars(0, ffd_unit_test);
initial $dumpfile("ffd_testbench.vcd");

Two functions follow, setup() and teardown(). Use them to configure the environment of the testcases:

• setup() is called before each testcase execution
• teardown() is called after each testcase execution

A testcase is enclosed between two specific defines:

`UNIT_TEST("TESTNAME")
    ...
`UNIT_TEST_END

TESTNAME is a string which will be displayed when test execution will start. Then you can use the macros provided to display information, warning, error and check some signals values. Each error encountered by a macro increments a globla error counter which determine a testsuite status. If the error counter is bigger than 0, the test is considered as failed.

A testsuite, comprising several UNIT_TEST, is declared with another define:

`TEST_SUITE("SUITENAME")
    ...
`TEST_SUITE_END

To test the FFD, add the next line into setup() to drive the reset and init the FFD input:

arstn = 1'b0;
d = 1'b0;
#100;
arstn = 1'b1;

and into the testcase:

`FAIL_IF(q);

Here is a basic unit test checking if the FFD output is 0 after reset. Once called svutRun in your shell, you should see something similar:

SVUT relies (optionally) on files.f to declare the fileset and define. Follows an example:

...
+define+MY_DEFINE_SIM1
+define+MY_DEFINE_SIM2=723
./ffd.sv
+incdir+$HOME/work/mylib
...

The user can also choose to pass define in the command line, common for both the simulator:

svutRun -test my_testbench.sv -define "DEF1=1;DEF2;DEF3=3"

SVUT doesn't check possible collision between define passed in command line and the others defined in files.f. Double check that point if unexpected behavior occurs during testbench.

Finally, SVUT supports VPI for Icarus. Follow an example to compile and set up the flow of an hypothetic UART, compiled with iverilog and using a define "PORT":

iverilog-vpi uart.c
svutRun -vpi "-M. -muart" -define "PORT=3333" -t ./my_testbench.sv &

Now you know the basics of SVUT. The generated testbench provides prototypes of available macros. Try them and play around to test SVUT. You can find these files into the example folder.

Enjoy!

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